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Research Spending & Results

Award Detail

Awardee:QCML LABS, LLC
Doing Business As Name:QCML LABS, LLC
PD/PI:
  • Behtash Behin-Aein
  • (765) 586-5936
  • behtash.behin.aein@gmail.com
Co-PD(s)/co-PI(s):
  • Supriyo Datta
Award Date:06/11/2021
Estimated Total Award Amount: $ 256,000
Funds Obligated to Date: $ 256,000
  • FY 2021=$256,000
Start Date:09/01/2021
End Date:08/31/2022
Transaction Type:Grant
Agency:NSF
Awarding Agency Code:4900
Funding Agency Code:4900
CFDA Number:47.041
Primary Program Source:040100 NSF RESEARCH & RELATED ACTIVIT
Award Title or Description:STTR Phase I: Room Temperature Implementation of Quantum Algorithms using Spintronics Technology
Federal Award ID Number:2035962
DUNS ID:117409577
Program:STTR Phase I
Program Officer:
  • Peter Atherton
  • (703) 292-8772
  • patherto@nsf.gov

Awardee Location

Street:108 SPINNING WHEEL CT
City:WEST LAFAYETTE
State:IN
ZIP:47906-2423
County:West Lafayette
Country:US
Awardee Cong. District:04

Primary Place of Performance

Organization Name:Purdue University
Street:610 Purdue Mall
City:West Lafayette
State:IN
ZIP:47907-2040
County:West Lafayette
Country:US
Cong. District:04

Abstract at Time of Award

The broader impact of this Small Business Technology Transfer (STTR) Phase I project will be to enable cheaper, faster, and more energy-efficient semiconductor chips dedicated to solving challenges with many possible outcomes and inherent uncertainty. Such problems are encountered in decision-making, risk management, chip design, drug design, business analytics, machine learning, computing failure rates of manufactured products, pricing complex financial derivatives, resource allocation in 5G networks and financial portfolios. Current methods for addressing these problems are intensive, time-consuming, and expensive. The proposed chips would quantify the uncertainty and find suitable solutions to many real-world challenges with faster, cheaper, and more energy-efficient methods. This Small Business Technology Transfer (STTR) Phase I project focuses on advancing probabilistic computers for probabilistic computing. Decision-making, econometrics, risk management, chip design, and drug development are not deterministic. By leveraging the natural stochasticity of specific devices, it is possible to dramatically reduce the number of devices otherwise used for the same computational tasks. The proposed computational architecture and pipelining enables improved computational speed, power consumption, and chip manufacturing costs. The goals of this project are two-fold. The first is to deliver 10-1000x improvement in computation speed compared to CPUs and GPUs using the emulation of probabilistic computers on Field Programmable Gate Arrays. The same task will make projections about the performance of the actual probabilistic computer. The second is to quantify how well the probabilistic computer can accommodate semiconductor manufacturing process variations. Controlling such variations is a significant factor in semiconductor manufacturing costs. This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.

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