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Research Spending & Results

Award Detail

Awardee:GEORGIA TECH RESEARCH CORPORATION
Doing Business As Name:Georgia Tech Research Corporation
PD/PI:
  • William Harris
  • (404) 894-4819
  • wharris@cc.gatech.edu
Co-PD(s)/co-PI(s):
  • Hadi Esmaeilzadeh
Award Date:07/29/2015
Estimated Total Award Amount: $ 237,148
Funds Obligated to Date: $ 237,148
  • FY 2015=$237,148
Start Date:09/01/2015
End Date:08/31/2017
Transaction Type:Grant
Agency:NSF
Awarding Agency Code:4900
Funding Agency Code:4900
CFDA Number:47.070
Primary Program Source:040100 NSF RESEARCH & RELATED ACTIVIT
Award Title or Description:STARSS: Small: Self-reliant Field-Programmable Gate Arrays
Federal Award ID Number:1526211
DUNS ID:097394084
Parent DUNS ID:097394084
Program:Secure &Trustworthy Cyberspace
Program Officer:
  • Nina Amla
  • (703) 292-7991
  • namla@nsf.gov

Awardee Location

Street:Office of Sponsored Programs
City:Atlanta
State:GA
ZIP:30332-0420
County:Atlanta
Country:US
Awardee Cong. District:05

Primary Place of Performance

Organization Name:Georgia Institute of Technology
Street:225 North Ave
City:Atlanta
State:GA
ZIP:30332-0002
County:Atlanta
Country:US
Cong. District:05

Abstract at Time of Award

Field-programmable gate arrays (FPGAs) are hardware circuits that can be reconfigured by a system user after being deployed. FPGAs are a compelling alternative architecture that may allow hardware performance to continue to improve at a dramatic rate. Unfortunately, systems that incorporate an FPGA may allow a potentially untrusted user to reprogram hardware after it has been deployed. Such a scenario enables novel security attacks that can leak a user's private information or corrupt critical information stored on a system, but are performed entirely in hardware. This project develops an approach for ensuring that FPGAs satisfy strong security policies even when programmed by an untrusted user that will incur no overheard for runtime performance. This research investigates techniques that automatically infer proofs of information-flow properties of circuits. This project designs and implements policy languages, proof languages, checking-circuit synthesizers, and proof generators, which in combination will dramatically improve the security of FPGA-based systems. These techniques will enable devices and data-centers to use FPGAs in novel circuit designs that satisfy strong, precise security guarantees and can be updated dynamically.

Publications Produced as a Result of this Research

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Amir Yazdanbakhsh and Divya Mahajan and Pejman Lotfi-Kamran and Hadi Esmaeilzadeh "AxBench: A Multi- Platform Benchmark Suite for Approximate Computing" Journal of Design and Test., v., 2016, p..

Amir Yazdanbakhsh and Gennady Pekhimenko and Bradley Thwaites and Hadi Esmaeilzadeh and Onur Mutlu and Todd Mowry "Mitigating the Memory Bottleneck with Approximate Load Value Prediction." IEEE Design and Test of Computers special issue on Approximate Computing (invited), v., 2016, p..

Amir Yazdanbakhsh and Gennady Pekhimenko and Bradley Thwaites and Hadi Esmaeilzadeh and Onur Mutlu and Todd Mowry "RFVP: Rollback-Free Value Prediction with Safe-to-Approximate Loads." ACM Transactions on Architecture and Code Optimization., v., 2016, p..

Amir Yazdanbakhsh and Jongse Park and Hardik Sharma and Pejman Lotfi-Kamran and Hadi Esmaeilzadeh "Neural Acceleration for GPU Throughput Processors" ACM/IEEE International Symposium on Microarchitecture (MICRO), v., 2015, p..

Atiyeh Lotfi and Abbas Rahimi and Amir Yazdanbakhsh and Hadi Esmaeilzadeh and Rajesh K. Gupta "Grater: An Approximation Workflow for Exploiting Data-Level Parallelism in {FPGA} Acceleration" ACM/IEEE Conference on Design Automation and Test in Europe (DATE), v., 2016, p..

Divya Mahajan and Amir Yazdanbakhsh and Jongse Park and Bradley Thwaites and Hadi Esmaeilzadeh "Towards Statistical Guarantees in Controlling Quality Tradeoffs for Approximate Acceleration." International Symposium on Computer Architecture (ISCA), v., 2016, p..

Divya Mahajan and Jongse Park and Emmanuel Amaro and Hardik Sharma and Amir Yazdanbakhsh and Joon Kim and Hadi Esmaeilzadeh "Tabla: A Unified Template-based Framework for Accelerating Statistical Machine Learning." IEEE International Symposium on High Performance Computer Architecture (HPCA), v., 2016, p..

Divya Mahajan and Jongse Park and Emmanuel Amaro and Hardik Sharma and Amir Yazdanbakhsh and Joon Kyung Kim and Hadi Esmaeilzadeh "TABLA: A Unified Template-based Framework for Accelerating Statistical Machine Learning." 22nd Annual IEEE International Symposium on High Performance Computer Architecture (HPCA), v., 2016, p..

Hardik Sharma and Jongse Park and Divya Mahajan and Emmanuel Amaro and Joon Kyung Kim and Chenkai Shao and Asit Mishra and Hadi Esmaeilzadeh "From High-Level Deep Neural Models to FPGAs" ACM/IEEE International Symposium on Microarchitecture (MICRO), v., 2016, p..

Jongse Park and Emmanuel Amaro and Divya Mahajan and Bradley Thwaites and Hadi Esmaeilzadeh "AxGames: Towards Crowdsourcing Quality Target Determination in Approximate Computing." International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), v., 2016, p..

Jongse Park and Hadi Esmaeilzadeh and Xin Zhang and Mayur Naik and William Harris "FlexJava: Language Support for Safe and Modular Approximate Programming." Joint Meeting of the European Software Engineering Conference and the ACM SIGSOFT Symposium on the Foundations of Software Engineering (ESEC/FSE), v., 2015, p..

Amir Yazdanbakhsh and Divya Mahajan and Pejman Lotfi-Kamran and Hadi Esmaeilzadeh "AxBench: A Multi-Platform Benchmark Suite for Approximate Computing" Journal of Design and Test, v., 2016, p..

Amir Yazdanbakhsh and Gennady Pekhimenko and Bradley Thwaites and Hadi Esmaeilzadeh and Onur Mutlu and Todd Mowry "Mitigating the Memory Bottleneck with Approximate Load Value Prediction" IEEE Design and Test of Computers special issue on Approximate Computing (invited), v.33, 2016, p.32-42.

Amir Yazdanbakhsh and Gennady Pekhimenko and Bradley Thwaites and Hadi Esmaeilzadeh and Onur Mutlu and Todd Mowry "RFVP: Rollback-Free Value Prediction with Safe-to-Approximate Loads" ACM Transactions on Architecture and Code Optimization, v., 2016, p..

Divya Mahajan Jongse Park Emmanuel Amaro Hardik Sharma Amir Yazdanbakhsh Joon Kyung Kim Hadi Esmaeilzadeh "TABLA: A Unified Template-based Framework for Accelerating Statistical Machine Learning" Appears in the Proceedings of the 22nd Annual IEEE International Symposium on High Performance Computer Architecture, v., 2016, p..

Hardik Sharma, Jongse Park, Emmanuel Amaro, Bradley Thwaites, Praneetha Kotha, Anmol Gupta, Joon Kyung Kim, Asit Mishra, Hadi Esmaeilzadeh "DNNWEAVER: From High-Level Deep Network Models to FPGA Acceleration" Workshop on Cognitive Architectures (CogArch) in conjunction with ASPLOS, v., 2016, p..


Project Outcomes Report

Disclaimer

This Project Outcomes Report for the General Public is displayed verbatim as submitted by the Principal Investigator (PI) for this award. Any opinions, findings, and conclusions or recommendations expressed in this Report are those of the PI and do not necessarily reflect the views of the National Science Foundation; NSF has not approved or endorsed its content.

 

As the demand for computation increases, the gains from general-purpose processors continue to diminish. To address this challenge, research in both academia and industry has begun to focus on developing programmable accelerators. Among programmable accelerators, Field-Programmable Gate Arrays (FPGAs) provide large gains in performance and energy efficiency. In particular, Microsoft has deployed FPGA’s in its data centers to accelerate its web-search service, Bing. Intel recently acquired a major FPGA vendor for 16.7 billion USD to integrate FPGAs in their data-center products and develop new platforms for Internet of Things (IoT) devices. Commercial products that integrate general-purpose cores (i.e., circuit design modules) with FPGAs have already been released by major chip producers and IoT design platforms based on FPGA’s are becoming available to crowds of developers. While FPGAs could provide significant benefits for designing next-generation systems, they present novel security issues that have not been adequately addressed. In particular, to implement highly optimized FPGA controllers, a host system typically provides direct read and write privileges to an FPGA. With such privileges, an FPGA can access critical system resources such as memory, the system bus, and even on-chip network devices without mediation from the operating system. As a consequence, an FPGA containing a security vulnerability, perhaps due to aggressive manual optimization, could constitute a critical target for leaking sensitive information throughout a host system. Moreover, practical core designs consist of complex submodules developed independently by multiple sources. If a single, commonly-used module leaks information in an unexpected way, it can affect the information-flow security of all cores designed to use it.

To address these challenges, we propose a domain-specific language, named STREAMS, for expressing information-flow policies with declassification over unbounded input streams. We also introduce a novel algorithm, named SIMAREL, that given a core design C and STREAMS policy P, automatically proves or falsifies that C satisfies P. The key technical insight behind the design of SIMAREL is a novel algorithm for efficiently synthesizing relational invariants over pairs of circuit executions. We expressed expected behavior of cores designed independently for research and production as STREAMS policies and used SIMAREL to check if each core satisfies its policy. SIMAREL proved that half of the cores satisfied expected behavior, but found unexpected information leaks in six open-source designs: an Ethernet controller, a flash memory controller, an SD-card storage manager, a robotics controller, a digital-signal processing (DSP) module, and a debugging interface.

Overall, the work supported with this project resulted in three papers in the most prestigious conference and journals of security and computer architecture. One the papers received the Distinguished Paper Award in HPCA 2016. The work also resulted in developing the very first open-source hardware acceleration frameworks for machine learning (http://act-lab.org/artifacts/tabla/) and AI/Deep Learning (http://act-lab.org/artifacts/dnnweaver/) that are being used across academia (e.g., UT Austin) and industry (e.g., Samsung). These artifacts, add tremendous value and credibility to our three publications that present novel ideas in programming languages, architecture and circuit design, software engineering, and machine learning.

Our solutions have had direct economic impact in the country as multiple startup companies are using our open-source solutions to develop commercial products. Furthermore, on the pedagogical side, not only we have trained PhD and Master students, but we have engaged undergraduate students directly in research and our work resulted in two undergraduate students to coauthor papers in the very top venues of computer architecture. These undergraduate students also won the Georgia Tech President's Undergraduate Research Award (PURA).

The project also enabled us to vigorously follow our plans to include minority and underrepresented students. The co-PI has been supervising one female PhD student, whose work, as the lead author, won the Distinguished Paper Award in HPCA 2016. Additionally, she won the 2017 National Center for Women & IT (NCWIT) Collegiate Award and the Grace Hopper Scholarship. She was also a finalist for the Qualcomm Innovation Fellowship in 2016. Moreover, the co-PI has already graduated a female and a Hispanic MS student. The female student joined Apple, while the Hispanic student has joined the PhD program at UC Berkeley. The Hispanic student co-authored three top-tier conference papers, including the aforementioned award-winning HPCA paper. Upon graduation, he was awarded the “College of Computing Marshall D. Williamson Fellowship Award” and “Georgia Tech’s Goizueta Foundation Fellowship.” Due to these extensive efforts in promoting diversity, Georgia Tech’s College of Computing awarded the co-PI the Lockheed Inspirational Young Faculty Award in 2016.

 

 


Last Modified: 11/13/2017
Modified by: Hadi Esmaeilzadeh

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