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Award Detail

Awardee:BRIGHAM YOUNG UNIVERSITY
Doing Business As Name:Brigham Young University
PD/PI:
  • Brent E Nelson
  • (801) 422-6455
  • nelson@ee.byu.edu
Co-PD(s)/co-PI(s):
  • Brad L Hutchings
  • Michael Rice
  • Michael J Wirthlin
Award Date:01/30/2008
Estimated Total Award Amount: $ 250,000
Funds Obligated to Date: $ 615,124
  • FY 2008=$83,275
  • FY 2013=$139,896
  • FY 2009=$70,000
  • FY 2012=$136,022
  • FY 2010=$150,931
  • FY 2011=$35,000
Start Date:02/01/2008
End Date:01/31/2016
Transaction Type:Grant
Agency:NSF
Awarding Agency Code:4900
Funding Agency Code:4900
CFDA Number:47.070
Primary Program Source:040100 NSF RESEARCH & RELATED ACTIVIT
Award Title or Description:BYU Site for CHREC I/UCRC
Federal Award ID Number:0801876
DUNS ID:009094012
Parent DUNS ID:001940170
Program:IUCRC-Indust-Univ Coop Res Ctr
Program Officer:
  • Thyagarajan Nandagopal
  • (703) 292-4550
  • tnandago@nsf.gov

Awardee Location

Street:A-285 ASB
City:Provo
State:UT
ZIP:84602-1231
County:Provo
Country:US
Awardee Cong. District:03

Primary Place of Performance

Organization Name:Brigham Young University
Street:A-285 ASB
City:Provo
State:UT
ZIP:84602-1231
County:Provo
Country:US
Cong. District:03

Abstract at Time of Award

This award establishes Brigham Young University (BYU) as a research site of the Industry/University Collaborative Research Center (IUCRC) for High-Performance Reconfigurable Computing. Other sites of this collaborative research center include the University of Florida (2007) and George Washington University (2007). Reconfigurable computing (RC) technology can be divided into two areas of use: High Performance Computing (HPC) and High Performance Embedded Computing (HPEC). RC technology is used in the field of HPC to accelerate demanding computations that would otherwise be performed in software on a large-scale computing system. RC technology is used in HPEC to create high-performance embedded computing solutions in areas such as signal and image processing, real-time vision, cryptography, and network processing. The mission of this center is to investigate, develop, and evaluate new concepts, methods, infrastructure, and tools in reconfigurable HPC and HPEC, from building-block devices to infrastructure to applications, and advance these technologies through research and education for the benefit of center members, students, and the discipline at large. The research BYU will address; 1) Novel Core Architectures and Related Components for Aerospace & Defense Applications, 2) Application Mapping of HPC Codes to High-Performance Reconfigurable Computing Systems, 3) Profiling, Analysis, & Performance Optimization for Reconfigurable Computing Applications, 4) Middleware, Interfaces, & other Infrastructure for High-Performance Reconfigurable Computers. The Center for High-Performance Reconfigurable Computing should significantly enhance the U.S. effort to maintain a strong leadership position within their area of information technology. It may also serve to bring industry and users together to define common standards. Industry members, researchers and students will gain from the interactions throughout the life of the research center. This should be a rewarding experience for all as the university has a detailed plan to achieve diversity in working with several minority institutions. Advances in RC affect virtually all disciplines of science and engineering which require high-performance computing, be it mainframe-oriented or embedded. RC technology promises to produce computing systems combining the flexibility of software-programmable computations with the computational power of custom hardware.

Publications Produced as a Result of this Research

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J. Bodily, B. Nelson, Z. Wei, D. Lee, and J. Chase "A Comparison Study on Implementing Optical Flow and Digital Communications on FPGAs and GPUs" ACM Transactions on Reconfigurable Technology and Systems (TRETS), v.3, 2010, p.. doi:doi.acm.org/10.1145/1754386.1754387 

Yubo Li, Brent Nelson, Michael Wirthlin "Synchronization Techniques for Crossing Multiple Clock Domains in FPGA-Based TMR Circuits" IEEE Transactions on Nuclear Science, v.57, 2010, p.3506. doi:10.1109/TNS.2010.2086075 

Yubo Li, Brent Nelson, Michael Wirthlin "Synchronization Techniques for Crossing Multiple Clock Domains in FPGA-Based TMR Circuits" IEEE Transactions on Nuclear Science, v.57, 2010, p.3506. doi:10.1109/TNS.2010.2086075 

J. Bodily, B. Nelson, Z. Wei, D. Lee, and J. Chase "A Comparison Study on Implementing Optical Flow and Digital Communications on FPGAs and GPUs" ACM Transactions on Reconfigurable Technology and Systems (TRETS),, v.3, 2010, p.6:1. doi:10.1145/1754386.1754387 

Christopher Lavin and Brent Nelson and Brad Hutchings "Improving Clock-Rate of Hard-Macro Designs" Proceedings of FPT'2013, v., 2013, p.246. doi:10.1109/FPT.2013.6718361 

Lamprecht, J.; Hutchings, B. "Profiling FPGA floor-planning effects on timing closure" International Conference on Field Programmable Logic and Applications (FPL), v.22, 2012, p.151. doi:10.1109/FPL.2012.6339254 

Nathan Rollins and Michael Wirthlin "Reliability of a Softcore Processor in a Commercial SRAM-based FPGA" Conference Publication, Published. Bibliography: FPGA 2012, v., 2012, p.171. doi:10.1145/2145694.2145723 

Y. Li, B. Nelson, M. Wirthlin "Reliability Models for SEC/DED Memory with Scrubbing in FPGA-based Designs" The International Conference on Radiation and its Effects on Components and Systems (RADECS), v., 2012, p.2720. doi:10.1109/TNS.2013.2251902 

Harding, A. and Ellsworth, K. and Nelson, B. and Wirthlin, M. "Characterization and Mitigation of the MGT-Based Aurora Protocol in a Radiation Environment" Radiation Effects Data Workshop (REDW), 2013 IEEE, v., 2013, p.1. doi:10.1109/REDW.2013.6658186 

Monson, J, Wirthlin, M, and Hutchings, B. L. "Implementing high-performance, low-power FPGA-based optical flow accelerators in C" Application-Specific Systems, Architectures and Processors (ASAP), 2013 IEEE 24th International, v., 2013, p.363. doi:10.1109/ASAP.2013.6567602 

Haroldsen, T.; Nelson, B.; White, B. "Rapid FPGA design prototyping through preservation of system logic: A case study" Field Programmable Logic and Applications (FPL), 2013 23rd International Conference, v., 2013, p.1. doi:10.1109/FPL.2013.6645539 

Lavin, C.; Nelson, B.; Hutchings, B. "Impact of hard macro size on FPGA clock rate and place/route time" Field Programmable Logic and Applications (FPL), 2013 23rd International Conference, v., 2013, p.1. doi:10.1109/FPL.2013.6645510 

M. Caffrey, M. Wirthlin, W. Howes, D. Richins, D. Roussel-Dupre, S. Robinson, A. Nelson, and A. Salazar "On-Orbit Flight Results from the Reconfigurable Cibola Flight Experiment Satellite (CFESat)" Proc. of 16th IEEE Symposium on Field- Programmable Custom Computing Machines (FCCM), v., 2009, p.3. doi:10.1109/FCCM.2009.22 

Brad Hutchings, Brent Nelson, Stephen West, Reed Curtis "Optical Flow on the Ambric Massively Parallel Processor Array (MPPA)" Proceedings of the 16th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM), v., 2009, p.141. doi:10.1109/FCCM.2009.21 

Jonathan Johnson, William Howes, Michael Wirthlin, Daniel McMurtrey, Michael Caffrey, Paul Graham and Keith Morgan "Using Duplication with Compare for On-line Error Detection in FPGA-based Designs" Published Collection: IEEE Aerospace Conference, v., 2008, p.1. doi:10.1109/AERO.2008.4526470 

Wirthlin, M.; Lee, D.; Swift, G.; Quinn, H. "A Method and Case Study on Identifying Physically Adjacent Multiple-Cell Upsets Using 28-nm, Interleaved and SECDED-Protected Arrays" IEEE Transactions on Nuclear Science, v.61, 2014, p.3080. doi:10.1109/TNS.2014.2366913 

Nathan Rollins and Michael Wirthlin "Software Fault-Tolerant Techniques for Softcore Processors in Commercial SRAM-Based FPGAs" Microprocessors and Microsystems, v., 2011, p.. doi:10.1145/2145694.2145723 

Yubo Li, Brent Nelson, Michael Wirthlin "Reliability Models for SEC/DED Memory with Scrubbing in FPGA-based Designs" IEEE Transactions on Nuclear Science, v.60, 2013, p.2720. doi:10.1109/TNS.2013.2251902 

Brian Pratt, Megan Fuller, Michael Wirthlin "Reduced-Precision Redundancy on FPGAs" International Journal on Reconfigurable Computing, v.2011, 2011, p.1. doi:10.1155/2011/897189 

B. Pratt, M. Fuller, M. Rice, and M. Wirthlin "Reduced ?Precision Redundancy for Reliable FPGA Communications Systems in High-Radiation Environments" IEEE Transactions on Aerospace and Electronic Systems, v.26, 2013, p.369. doi:10.1109/TAES.2013.6404109 

Michael Wirthlin "FPGAs operating in a radiation environment: lessons learned from FPGAs in space" IOP Science Journal of Instrumentation, v.8, 2013, p.1. doi:10.1088/1748-0221/8/02/C02020 

Michael Wirthlin, Helio Takai, and Alex Harding "Soft Error rate estimations of the Kintex-7 FPGA within the ATLAS Liquid Argon (LAr) Calorimeter" IOP Science Journal of Instrumentation, v.9, 2014, p.1. doi:10.1088/1748-0221/9/01/C01025 

Joshua Monson and Brad Hutchings "New Approaches for In-System Debug of Behaviorally-synthesized FPGA Circuits" Proceedings of International Conference on Field-Programmable Logic and Applications, v., 2014, p.1. doi:10.1109/FPL.2014.6927495 

Monson, J, Wirthlin, M, and Hutchings, B.L. "Optimization techniques for a high level synthesis implementation of the Sobel filter" 2013 International Conference on Reconfigurable Computing and FPGAs (ReConFig), v., 2013, p.1. doi:10.1109/ReConFig.2013.6732315 

Christopher Lavin, Brent Nelson, Brad Hutchings "Improving Clock-Rate of Hard-Macro Designs" Proceedings of the 2013 International Conference on Field-Programmable Technology (ICFPT 13), v., 2013, p.1. doi:10.1109/FPL.2013.6645510 

Lee, David S.; Wirthlin, Michael; Swift, Gary; Le, Anthony C. "Single-Event Characterization of the 28 nm Xilinx Kintex-7 Field-Programmable Gate Array under Heavy Ion Irradiation" Radiation Effects Data Workshop (REDW), v., 2014, p.1. doi:10.1109/REDW.2014.7004595 

Nathaniel Rollins and Adam Arnesen and Michael Wirthlin "An XML Schema for Representing Reusable IP Cores for Reconfigurable Computing" Proceedings of the National Aerospace and Electronics Conference (NAECON 2008), v., 2008, p.190. doi:10.1109/NAECON.2008.4806545 

B. Pratt, M. Wirthlin, M. Caffrey, P. Graham, and K. Morgan "Noise Impact of Single-Event Upsets on an FPGA-Based Digital Filter" Proc. of Intl. Conference on Field-Programmable Logic and Applications (FPL), v., 2009, p.38. doi:10.1109/FPL.2009.5272554 

A. Arnesen, N. Rollins, and M. Wirthlin "A Multi-Layered XML Schema and Design Tool for Reusing and Integrating FPGA IP" Proc. of Intl. Conference on Field-Programmable Logic and Applications (FPL), v., 2009, p.472. doi:10.1109/FPL.2009.5272468 

B. Hutchings, B. Nelson, S. West, and R. Curtis "Comparing Fine-Grained Performance on the Ambric MPPA Against an FPGA" Proc. of Intl. Conference on Field- Programmable Logic and Applications (FPL), v., 2009, p.174. doi:10.1109/FPL.2009.5272505 

M. Rice, M. Padilla, and B. Nelson "On FM Demodulators in Software- Defined Radios Using FPGAs" Proc. of Military Communications Conference (MILCOM), v., 2009, p.1. doi:10.1109/MILCOM.2009.5379759 

Y. Li, B. Nelson, and M. Wirthlin "Synchronization Issues of TMR Crossing Multiple Clock Domains" Proc. of Military and Aerospace Programmable Logic Devices Conference (MAPLD), v., 2009, p.3506. doi:10.1109/TNS.2010.2086075 

J. Anderson, B. Nelson, and M. Wirthlin "Reduced Cost Reliability via Statistical Model Detection" Proc. of Military and Aerospace Programmable Logic Devices Conference (MAPLD), v., 2009, p.1. doi:10.1109/AERO.2010.5446660 

C. Lavin, M. Padilla, J. Lamprecht, P. Lundrigan, B. Nelson, and B. Hutchings "Rapid Prototyping Tools for FPGA Designs: RapidSmith" "Proc. of International Conference on Field-Programmable Technology (FPT) ", v., 2010, p.353. doi:10.1109/FPT.2010.5681429 

A. Arnesen, K. Ellsworth, D. Gibelyou, T. Haroldsen, J. Havican, M. Padilla, B. Nelson, M. Rice, and M. Wirthlin "Increasing Design Productivity Through Core Reuse, Meta-Data Encapsulation, and Synthesis" Proc. of International Conference on Field-Programmable Logic and Applications (FPL), v., 2010, p.538. doi:10.1109/FPL.2010.106 

C. Lavin, M. Padilla, S. Ghosh, B. Nelson, B. Hutchings, and M. Wirthlin "Using Hard Macros to Reduce FPGA Compilation Time" "Proc. of International Conference on Field-Programmable Logic and Applications (FPL) ", v., 2010, p.438. doi:10.1109/FPL.2010.90 

B. Pratt, M. Fuller, M. Rice, and M. Wirthlin ""Reliable Communications Using FPGAs in High-Radiation Environments - Part I: Characterization"" Proc. of IEEE International Conference on Communications (ICC), v., 2010, p.1. doi:10.1109/ICC.2010.5502571 

N. Rollins, M. Fuller, and M. Wirthlin "A Comparison of Fault-Tolerant Memories in SRAM-Based FPGAs" Proc. of IEEE Aerospace Conference (AERO), v., 2010, p.1. doi:10.1109/AERO.2010.5446661 

J. Anderson, B. Nelson, and M. Wirthlin ""Using Statistical Models with Duplication and Compare for Reduced Cost FPGA Reliability "" Proc. of IEEE Aerospace Conference (AERO), v., 2010, p.1. doi:10.1109/AERO.2010.5446660 

J. Johnson and M. Wirthlin ""Voter Insertion Algorithms for FPGA Designs Using Triple Modular Redundancy"" Proc. of ACM SIGDA Interntional Symposium on Field-Programmable Gate Arrays (FPGA), v., 2010, p.249. doi:10.1145/1723112.1723154 

Kevin Ellsworth, Travis Haroldsen, Brent Nelson, and Michael Wirthlin "Dual Channel Architecture for Reliable FPGA high Speed Serial Links" Proceedings of the 2011 IEEE Aerospace Conference, v., 2011, p.1. doi:10.1109/AERO.2011.5747458 

Christopher Lavin, Marc Padilla, Jaren Lamprecht, Philip Lundrigan, Brent Nelson and Brad Hutchings "HMFlow: Accelerating FPGA Compilation with Hard Macros for Rapid Prototyping" Proceedings of The 19th Annual IEEE International Symposium on Field- Programmable Custom Computing Machines (FCCM?11), v., 2011, p.117. doi:10.1109/FCCM.2011.17 

Christopher Lavin, Marc Padilla, Jaren Lamprecht, Philip Lundrigan, Brent Nelson, Brad Hutchings "RapidSmith: Do-It-Yourself CAD Tools for Xilinx FPGAs" "Proceedings of the 21st International Conference on Field Programmable Logic and Applications (FPL'2011) ", v., 2011, p.349. doi:10.1109/FPL.2011.69 

Subhrashanka Ghosh, Brent Nelson "XDL-Based Module Generators for Rapid FPGA Design Implementation" ": Proceedings of the 21st International Conference on Field Programmable Logic and Applications (FPL'2011) ", v.21, 2011, p.64. doi:10.1109/FPL.2011.22 

N. Rollins and M. Wirthlin ""Software Fault-Tolerant Techniques for Softcore Processors in Commercial SRAM-Based FPGAs"" Proc. of 1st Workshop on Software- Controlled, Adaptive Fault-Tolerance in Microprocessors (SCAFT), v.24, 2011, p.. doi:10.1145/2145694.2145723 


Project Outcomes Report

Disclaimer

This Project Outcomes Report for the General Public is displayed verbatim as submitted by the Principal Investigator (PI) for this award. Any opinions, findings, and conclusions or recommendations expressed in this Report are those of the PI and do not necessarily reflect the views of the National Science Foundation; NSF has not approved or endorsed its content.

FPGA devices applied to high performance computing fill an important and growing niche between custom integrated circuits (micro-chips) on the one hand and programmable processors (CPUs) on the other. Like CPUs, FPGAs are flexible and can be used to perform a variety of different functions.  Also like CPUs they can be rapidly reprogrammed to perform these new computations and functions even after they have been deployed into the field in larger electronics systems.  Like custom integrated circuits, FPGAs provide much higher performance than that achievable using a CPU, a significant advantage in demanding application areas.  However, FPGAs have two significant disadvantages compare to both CPUs and custom integrated circuits.

The first disadvantage is that creating a new design to run on an FPGA circuit is a very time consuming activity and requires skills very different from those required to do software programming.  These skills are in relatively short supply and require engineers trained in digital circuit design via a degree in either Electrical or Computer Engineering.  The B1 series of projects during Phase I of BYU’s involvement in CHREC were focused on reducing the design effort (and thus design time) associated with using FPGAs to implement digital systems.  This was done via a series of projects which focused on providing higher level abstractions to elevate the designer above the myriad of circuit details associated with hardware design and to enable the use of CAD tools for performing many of the time consuming tasks associated with hardware design.  The resulting design methods could achieve a 70x reduction in design time and, more importantly, potentially reduce the need for trained hardware engineers as designers.  The impact of this work, then, is that it promises to enable non-hardware engineers (and perhaps software programmers) to make use of FPGA technology in ways never before allowed.

The second disadvantage of FPGA technology relates to its use in radiation environments (such as might be encountered in space). The B2 and B5 series of projects developed a number of techniques, tools, and approaches to facilitate the reliable operation of reconfigurable systems in space and other harsh environments. Several of these techniques have been launched into orbit and validated in operating spacecraft (for example, the Cibola Flight Experiment (CFE) developed by Los Alamos National Laboratory and the MISSE-8 experiment developed by Sandia National Laboratories). The success of these techniques has been recognized by a number of partners who have used these techniques and tools to facilitate the design of their own spacecraft exploiting reconfigurable hardware. This work is also being adopted by some high-energy physics experiments and commercial users of FPGAs who need high-reliable reconfigurable systems operating on earth.

The center has been especially successful at involving students in the sponsored research activities of all center proejcts. During the course of this award, 62 students have participated in a mentored research project that includes a faculty mentor and specific research task. The majority of these started their research efforts as undergraduate students and many continued participation as graduate students. During the course of this phase of the center, 49 peer-reviewed papers were published at a variety of conferences and academic journals. In addition, four PhD dissertations and twelve masters thesis were completed.

The center has also been very active in a number of community outreach programs to encourage interest in engineering careers. Undergraduate students working in the center helped develop and manage the BYU "Chip Camp" summer program. This program involves girls and boys who have completed seventh or eighth grade and provides hands-on science ac...

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