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Research Spending & Results

Award Detail

Awardee:VIRGINIA POLYTECHNIC INSTITUTE & STATE UNIVERSITY
Doing Business As Name:Virginia Polytechnic Institute and State University
PD/PI:
  • Peter M Athanas
  • (540) 392-7250
  • athanas@vt.edu
Co-PD(s)/co-PI(s):
  • Wuchun Feng
Award Date:12/27/2007
Estimated Total Award Amount: $ 250,000
Funds Obligated to Date: $ 618,190
  • FY 2011=$35,000
  • FY 2009=$113,268
  • FY 2012=$135,893
  • FY 2010=$150,931
  • FY 2008=$183,098
Start Date:01/01/2008
End Date:12/31/2014
Transaction Type:Grant
Agency:NSF
Awarding Agency Code:4900
Funding Agency Code:4900
CFDA Number:47.041
Primary Program Source:040100 NSF RESEARCH & RELATED ACTIVIT
Award Title or Description:I/UCRC Proposal For University Site At Virginia Tech: Center For High-Performance Reconfigurable Computing (CHREC)
Federal Award ID Number:0804155
DUNS ID:003137015
Parent DUNS ID:003133790
Program:IUCRC-Indust-Univ Coop Res Ctr
Program Officer:
  • Thyagarajan Nandagopal
  • (703) 292-4550
  • tnandago@nsf.gov

Awardee Location

Street:Sponsored Programs 0170
City:BLACKSBURG
State:VA
ZIP:24061-0001
County:Blacksburg
Country:US
Awardee Cong. District:09

Primary Place of Performance

Organization Name:Virginia Polytechnic Institute and State University
Street:Sponsored Programs 0170
City:BLACKSBURG
State:VA
ZIP:24061-0001
County:Blacksburg
Country:US
Cong. District:09

Abstract at Time of Award

This award establishes Virginia Polytechnic Institute as a research site of the Industry/University Collaborative Research Center (IUCRC) for High-Performance Reconfigurable Computing. Other sites of this collaborative research center include the University of Florida (2007), George Washington University (2007), and Brigham Young University (2008). Reconfigurable computing (RC) technology can be divided into two areas of use: High Performance Computing (HPC) and High Performance Embedded Computing (HPEC). RC technology is used in the field of HPC to accelerate demanding computations that would otherwise be performed in software on a large-scale computing system. RC technology is used in HPEC to create high-performance embedded computing solutions in areas such as signal and image processing, real-time vision, cryptography, and network processing. The mission of this center is to investigate, develop, and evaluate new concepts, methods, infrastructure, and tools in reconfigurable HPC and HPEC, from building-block devices to infrastructure to applications, and advance these technologies through research and education for the benefit of center members, students, and the discipline at large. The research BYU will address; 1) Novel Core Architectures and Related Components for Aerospace & Defense Applications, 2) Application Mapping of HPC Codes to High-Performance Reconfigurable Computing Systems, 3) Profiling, Analysis, & Performance Optimization for Reconfigurable Computing Applications, 4) Middleware, Interfaces, & other Infrastructure for High-Performance Reconfigurable Computers. The Center for High-Performance Reconfigurable Computing should significantly enhance the U.S. effort to maintain a strong leadership position within their area of information technology. It may also serve to bring industry and users together to define common standards. Industry members, researchers and students will gain from the interactions throughout the life of the research center. Advances in RC affect virtually all disciplines of science and engineering which require high-performance computing, be it mainframe-oriented or embedded. RC technology promises to produce computing systems combining the flexibility of software-programmable computations with the computational power of custom hardware.

Publications Produced as a Result of this Research

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Jorge Suris, Adolfo Recio, Peter Athanas "Rapid Radio: Human-Assisted Signal Classification and Receiver Implementation" Software Defined Radio Forum, Washington D.C, 2008, v., 2008, p..

M. Gardner, P. Sathre, W. Feng, G. Martinez "Characterizing the Challenges and Evaluating the Efficacy of a CUDA-to-OpenCL Translator" Parallel Computing, v.39, 2013, p.769. doi:http://dx.doi.org/10.1016/j.parco.2013.09.003 

R. Anandakrishnan, T. Scogland, A. Fenley, J. Gordon, W. Feng, and A. Onufriev "Accelerating Electrostatic Surface Potential Calculation with Multiscale Approximation on Graphics Processing Units" Journal of Molecular Graphics Modelling (JMGM), v.28, 2010, p.904.

A. Aji and W. Feng "Optimizing Performance, Cost, and Sensitivity in Pairwise Sequence Search on a Cluster of PlayStations" IEEE International Conference on BioInformatics and BioEngineering, v., 2008, p..

T. Scogland, H. Lin, and W. Feng "A First Look at Integrated GPUs for Green High-Performance Computing" Proc. of International Conference on Energy-Aware High-Performance Computing (EnA-HPC), v., 2010, p..

R. Anandakrishnan and T. Scogland and A. Fenley and J. Gordon and W. Feng and A. Onufriev "Accelerating Electrostatic Surface Potential Calculation with Multiscale Approximation on Graphics Processing Units" Journal of Molecular Graphics Modelling ({JMGM}), v.28, 2010, p.904.

M. Gardner and P. Sathre and W. Feng and G. Martinez "Characterizing the Challenges and Evaluating the Efficacy of a {CUDA}-to-OpenCL Translator" Parallel Computing: Special Issue, v., 2013, p..


Project Outcomes Report

Disclaimer

This Project Outcomes Report for the General Public is displayed verbatim as submitted by the Principal Investigator (PI) for this award. Any opinions, findings, and conclusions or recommendations expressed in this Report are those of the PI and do not necessarily reflect the views of the National Science Foundation; NSF has not approved or endorsed its content.

In its first six years of operation, CHREC has been one of the most successful Phase-I I/UCRC centers at NSF. Despite economic recession and other national setbacks, CHREC has grown since 2007 to have more than 40 full memberships with almost 30 industry members during Phase 1. Scholarship has been strong throughout this period, in terms of refereed journal and conference publications. Graduations, especially Ph.D. and M.S. students, have also been strong. Our industry members are very pleased with CHREC and find it to be highly effective in terms of R&D achievement, technology transfer, recruiting, and return on investment.

The value attained by the CHREC Center is of major significance to all participants. For NSF, its mission to “promote the progress of science,” to “advance the national health, prosperity, and welfare,” and to “secure the national defense” is directly supported at minimal cost. For the university sites, their mission of success in basic and applied research with high-quality graduate education is fulfilled. For the industry members of the Center, their research and development needs are directly addressed by the research thrusts of the Center and specific tasks within each thrust, typically at a small fraction of the cost of pursuing and funding the same tasks outside of the Center. Each industry member of CHREC plays a key role in selecting and monitoring tasks of mutual interest, and ultimately reaping the benefits of the research via technology transfer and student recruitment to industry and ultimately the marketplace. 

The Virginia Tech CHREC site, through the support of the industrial affiliates and the National Science Foundation, has completed several projects, and worked with the affiliates in transferring the technology.  The projects include:

  • V1-08: Model-Based Engineering Framework for HPRC Applications
  • V2-08: Process-to-Core Mapping for Advanced Architectures
  • V3-08: Advancing HPRC Development Environments
  • V1-09: Characterizing and Optimizing Emerging Devices
  • V3-09: Autonomous Adaptive Systems
  • V1-10: On the Performance, Programmability, and Power of Accelerators
  • V1-11: On the Performance, Programmability, and Power of Accelerators
  • V2-11- Back-end Productivity Enhancements for HPC

For specific questions or comments about this information including the NSF Project Outcomes Report, contact us.