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Lowering Energy Consumption of Large Data Caches

NSF Award:

CPA-CSA: Algorithms and Implementations for Scalable Transactional Memory  (University of Utah)

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In an NSF-sponsored project, computer scientists at the University of Utah have developed techniques to reduce the energy consumption associated with large, temporary storage areas, called caches.

The innovation could significantly lower energy consumption and improve performance within multi-core processors, directly impacting future computing devices including laptops, desktops and server processors.

The group explored the use of algorithms to reduce on-chip communication time, while also exploring ways to change wiring patterns for improved energy efficiency.

In the near future, processors will incorporate tens to hundreds of cores and large caches as well as complex on-chip networks to connect these systems. In such architectures, during tasks and necessary checks for operation, a large fraction of processor delay and power use will occur within the on-chip network.

By combining algorithms and a wiring technique known as low-swing wires, Professor Rajeev Balasubramonian's group showed that limited use of low-swing wires can yield compelling improvements in terms of performance and power.


  • Diagram of wiring within a large cache bank
Heterogeneous low-energy and high-performance wiring within a large cache bank
Rajeev Balasubramonian, University of Utah

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