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Award Detail

Doing Business As Name:Washington State University
  • Subhanshu Gupta
  • (509) 335-5045
Award Date:12/06/2019
Estimated Total Award Amount: $ 500,000
Funds Obligated to Date: $ 402,820
  • FY 2020=$402,820
Start Date:03/01/2020
End Date:02/28/2025
Transaction Type:Grant
Awarding Agency Code:4900
Funding Agency Code:4900
CFDA Number:47.041
Primary Program Source:040100 NSF RESEARCH & RELATED ACTIVIT
Award Title or Description:CAREER: Scalable and reconfigurable time-based circuits and systems for high-resolution large antenna arrays
Federal Award ID Number:1944688
DUNS ID:041485301
Parent DUNS ID:041485301
Program:CCSS-Comms Circuits & Sens Sys
Program Officer:
  • Jenshan Lin
  • (703) 292-7950

Awardee Location

Street:280 Lighty
Awardee Cong. District:05

Primary Place of Performance

Street:355 NE Spokane St, EME 102A
Cong. District:05

Abstract at Time of Award

Extremely large antenna arrays (LAA) comprising hundreds of antenna elements promise to provide unprecedented spatial resolutions that can not only enable many critical infrastructure technologies using millimeter-wave wireless communications but also usher in exciting concepts such as holographic surfaces for multi-user wireless communications, six-dimensional positioning for autonomous vehicles, high-speed communication links for deep-space planetary explorations, and automobile radars for detecting multiple objects. However, the signal processing at these large-scale arrays bring challenges of higher energy consumption and less accurate localization. Conventional phased array transceivers, which interface with the real-world signals, face several impediments in low-latency tracking and scaling due to highly complex signal processing and imperfect spatial filtering. Such imperfections result in drastic performance degradation endangering evolution of emerging wireless technologies. To overcome these fundamental challenges, this research seeks to use discrete-time delay-compensating techniques incorporating scalable time-based circuits and systems so that future LAAs can estimate direction-of-arrival precisely, cancel multiple interferences efficiently, and optimize the physical front-end transceivers autonomously. This research effort is integrated with the principal investigator's educational career goal of enhancing high-school and undergraduate learning experience by increasing education, awareness and preparation of the students through active collaborations with national labs and industry. The objective of this research is to transform multi-antenna phased arrays using discrete-time delay-compensating time-based circuits and systems with wide delay ranges and high precision for both energy-efficient spatial signal processing and low-latency beam acquisition. Several design techniques with non-uniform-sampling-based scalable discrete-time data converters will form the basis of delay-compensating spatial signal processor capable of handling gigahertz signal bandwidth. First, a discrete-time delay-compensating spatial signal processor will be demonstrated with variable gain and delay ranges for near-field and far-field LAAs. Second, the delay-compensating technique will be instituted in linear time-based matrix-multiplying data converters optimized using artificial-intelligence based self-initializing bias optimization techniques to demonstrate faster and energy-efficient convergence. Third, scalable system-level models for spatial arrays incorporating wide scan angles, high-speed signal bandwidth, large number of antenna elements, low-latency direction-of-arrival, and segmentation in true-time-delay arrays will be developed to study their effects on both spectral efficiency and energy efficiency for future LAAs. Through these comprehensive studies, the project will establish the advantages of discrete-time delay-compensating in wideband LAAs. This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.

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